Method of fabricating semiconductor device

ABSTRACT

The object of the present invention is to provide a semiconductor device having small mounting area with reduced cost.  
     A board with a plurality of device carrier areas thereon and an electrode pattern serving as external electrodes on a back of the board is prepared, and semiconductor chips are fixed respectively to the device carrier areas. The semiconductor chips fixed to the device carrier areas are covered with a common resin layer. A round surface of the common resin layer is flattened into a flat and horizontal surface, and a dicing sheet is applied to the flat and horizontal surface of the common resin layer with the electrode pattern facing upwardly. The board and the common resin layer are separated into segments including the device carrier areas thereby to produce individual semiconductor devices by dicing from the back of the board.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a method of fabricating asemiconductor device, and more particularly to a method of fabricating asemiconductor device having a reduced package contour, a reducedmounting area, and a reduced cost.

[0003] 2. Description of the Related Art

[0004] In the fabrication of semiconductor devices, it has beencustomary to separate semiconductor chips from a wafer by dicing, fixingthe semiconductor chips to a lead frame, sealing the semiconductor chipsfixed to the lead frame with a mold and a synthetic resin according to atransfer molding process, and dividing the sealed semiconductor chipsinto individual semiconductor devices. The lead frame comprises arectangular or hooped frame. A plurality of semiconductor devices aresimultaneously sealed in one sealing process.

[0005]FIG. 1 of the accompanying drawings illustrates a conventionaltransfer molding process. In the conventional transfer molding process,a lead frame 2 to which semiconductor chips 1 are fixed by die bondingand wire bonding is placed in a cavity 4 defined by upper and lowermolds 3A, 3B. Epoxy resin is then poured into the cavity 4 to seal thesemiconductor chips 1. After the transfer molding process, the leadframe 2 is cut off into segments containing the respective semiconductorchips 1, thus producing individual semiconductor devices. For moredetails, reference should be made to Japanese laid-open patentpublication No. 05-129473, for example.

[0006] Actually, as shown in FIG. 2 of the accompanying drawings, thelower mold 3B has a number of cavities 4 a-4 f, a source 5 of syntheticresin, a runner 6 connected to the source 5 of synthetic resin, andgates 7 for pouring the synthetic resin from the runner 6 into thecavities 4 a-4 f. The cavities 4 a-4 f, the source 5 of synthetic resin,the runner 6, and the gates 7 are all in the form of recesses andgrooves defined in the surface of the lower mold 3B. If the lead frame 2is of a rectangular shape, then ten semiconductor chips 1 are mounted onone lead frame, and the lower mold 3B has ten cavities 4, ten gates 7,and one runner 6 per lead frame. The entire lower mold 3B has as many ascavities 4 as necessary for twenty lead frames 2, for example.

[0007]FIG. 3 of the accompanying drawings shows a semiconductor devicefabricated by the conventional transfer molding process. As shown inFIG. 3, a semiconductor chip 1 containing components such as transistorsis fixedly mounted on an island 8 of a lead frame by a bonding material9 such as solder. The semiconductor chip 1 has electrode pads connectedto leads 10 by wires 11, and has its peripheral portions covered with amolded body 12 of synthetic resin which is defined in shape by thecavity 4. The leads 10 have respective distal ends projecting out of themolded body 12 of synthetic resin.

[0008] In the conventional semiconductor package shown in FIG. 3, sincethe leads 10 for connection to external circuits project from the moldedbody 12 of synthetic resin, dimensions of the package that extend up tothe projecting distal ends of the leads 10 need to be considered ascovering a mounting area of the package. Therefore, the mounting area ofthe package is much larger than the contour of the molded body 12 ofsynthetic resin.

[0009] Furthermore, according to the conventional transfer moldingprocess, since the molded body 12 of synthetic resin is hardened whileit is being placed under pressure, the synthetic resin is also hardenedin the runner 6 and the gates 7, and the hardened synthetic resin in therunner 6 and the gates 7 has to be thrown away. Because the gates 7 arerequired for respective individual semiconductor devices to befabricated, the synthetic resin is not utilized highly efficiently, butthe number of semiconductor devices that can be fabricated is smallrelatively to the amount of synthetic resin consumed.

SUMMARY OF THE INVENTION

[0010] It is therefore an object of the present invention to provide asemiconductor device having a small size with relatively small mountingarea.

[0011] Another object of the present invention is to provide a method offabricating a semiconductor device relatively inexpensively.

[0012] According to the present invention, there is provided a method offabricating a semiconductor device, comprising the steps of preparing aboard with a plurality of device carrier areas thereon, fixingsemiconductor chips respectively to the device carrier areas, coveringthe semiconductor chips fixed to the device carrier areas with a commonresin layer, flattening a surface of the common resin layer, applying adicing sheet to the flattened surface of the common resin layer, andseparating the board and the common resin layer into segments includingthe device carrier areas thereby to produce individual semiconductordevices by dicing from a back of the board.

[0013] The method may further comprise the step of placing an electrodepattern serving as external electrodes of the semiconductor chips on theback of the board, the electrode pattern being spaced inwardly fromdicing lines along edges of the segments so as to be kept out of contactwith a dicing blade along the dicing lines.

[0014] The above and other objects, features, and advantages of thepresent invention will become apparent from the following descriptionwhen taken in conjunction with the accompanying drawings whichillustrate a preferred embodiment of the present invention by way ofexample.

BRIEF DESCRIPTION OF THE DRAWINGS

[0015]FIG. 1 is a cross-sectional view illustrative of a conventionaltransfer molding process;

[0016]FIG. 2 is a plan view illustrative of the conventional transfermolding process;

[0017]FIG. 3 is a cross-sectional view of a semiconductor devicefabricated by the conventional transfer molding process;

[0018]FIG. 4 is a perspective view illustrative of a method offabricating a semiconductor device according to the present invention;

[0019]FIGS. 5A and 5B are plan and cross-sectional views, respectively,illustrative of the method of fabricating a semiconductor deviceaccording to the present invention;

[0020]FIG. 6 is a plan view illustrative of the method of fabricating asemiconductor device according to the present invention;

[0021]FIGS. 7A, 7B, and 7C are cross-sectional views illustrative of themethod of fabricating a semiconductor device according to the presentinvention;

[0022]FIGS. 8A and 8B are cross-sectional views illustrative of themethod of fabricating a semiconductor device according to the presentinvention; and

[0023]FIGS. 9A and 9B are perspective views of a semiconductor devicefabricated by the method according to the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

[0024] A method of fabricating a semiconductor device according to thepresent invention will be described below in terms of successive stepsthereof with reference to FIGS. 4 through 8A, 8B.

[0025] 1ST STEP

[0026] First, as shown in FIG. 4, a large-size board 21 having atwo-dimensional matrix of 100 device carrier areas 20 each correspondingto a semiconductor device is prepared. The board 21 comprises one ormore insulating boards of ceramics, glass epoxy, or the like, and has atotal thickness ranging from 200 to 350 μm to provide a mechanicalstrength large enough to withstand stresses imposed during thefabrication process.

[0027] An electrically conductive pattern made of printed metal paste oftungsten or the like and electroplated gold is formed on the surface ofeach of the device carrier areas 20. An electrode pattern of electrodesfor external connection is formed on the back of the board 21.

[0028]FIG. 5A shows in plan an electrically conductive pattern formed onthe face of the board 21, and FIG. 5B shows a cross section of the board21.

[0029] Each o f the device carrier areas 20, enclosed by the dottedlines, has a rectangular shape having a longer side which is 1.0 mm longand a shorter side which is 0.8 mm long. The device carrier areas 20 arearranged in a two dimensional matrix, and adjacent ones of the devicecarrier areas 20 are spaced from each other by a distance ranging from20 to 50 μm. The spacing between adjacent ones of the device carrierareas 20 serves as a dicing line 24 in a subsequent step. In each of thecarrier areas 20, the electrically conductive pattern provides an island25 and leads 26. The electrically conductive pattern segments in thedevice carrier areas 20 are identical in shape to each other.

[0030] The island 25 is a region where a semiconductor chip is to bemounted, and the leads 26 are to be connected by wires to electrode padsof a semiconductor chip on the island 25. Two first joint arms 27, eachhaving a width of 0.1 mm, for example, much smaller than the width ofthe island 25, extend continuously from the island 25 across the dicingline 24 to the leads 26 of an adjacent device carrier area 20. Twosecond joint arms 28 extend continuously from the respective leads 26 indirections perpendicular to the first joint arms 27 across the dicinglines 24 to the leads 26 of adjacent device carrier areas 20. Some ofthe second joint arms 28 are connected to a common joint 29 extendingaround the device carrier areas 20. The first and second joint arms 27,28 which are thus extended and connected electrically connect theislands 25 and the leads 26 to each other.

[0031] As shown in FIG. 5B, the board 21 has through holes 30 defined ineach of the device carrier areas 20. An electrically conductive materialsuch as tungsten is filled in the through holes 30. External electrodes31 are formed on the back of the board 21 in alignment with therespective through holes 30.

[0032]FIG. 3 shows in plan the reverse side of the board 21,illustrating a pattern of the external electrodes which are designatedby 31 a, 31 b, 31 c, 31 d. The external electrodes 31 a, 31 b, 31 c, 31d, which are independent of each other, are spaced or retracted adistance ranging from 0.05 to 0.1 mm inwardly from the edges of each ofthe device carrier areas 20, and electrically connected to the commonjoint 29 via the through holes 30. With this arrangement, a plated layerof gold of the electrically conductive pattern can be formed by theelectroplating process which employs the electrically conductive patternas one electrode. Only the first and second joint arms 27, 28 of thenarrow width extend across the dicing lines 24.

[0033] 2ND STEP (FIG. 7A)

[0034] Semiconductor chips 33 are mounted on the respective devicecarrier areas 20 of the common board 21 with the plated layer of gold,by die bonding and wire bonding. Specifically, the semiconductor chips33 are fixed to the surfaces of the islands 25 by an adhesive such as anAg paste, and the electrode pads of the semiconductor chips 33 areconnected to the leads 26 by wires 34. The semiconductor chips 33comprise three-terminal active components such as bipolar transistors,power MOSFETs, or the like. If the semiconductor chips 33 comprisebipolar transistors, then the external electrodes 31a, 31b serve ascollector terminals, and the external electrodes 31 c, 31 d serve asbase and emitter electrodes, respectively.

[0035] 3RD STEP (FIG. 7B)

[0036] A predetermined amount of liquid epoxy resin is dropped from adispenser (not shown) delivered to a position over the board 21 bypotting to cover all the semiconductor chips 33 with a common resinlayer 35. For example, if 100 semiconductor chips 33 are mounted on oneboard 21, then all the 100 semiconductor chips 33 are covered with thecommon resin layer 35. The liquid epoxy resin may be CV576AN(manufactured by Matsushita Electric Works, Ltd.). Since the droppedliquid epoxy resin is relatively highly viscous and has a surfacetension, the common resin layer 35 has a round surface.

[0037] 4TH STEP (FIG. 7C)

[0038] After the dropped liquid resin is cured at a temperature rangingfrom 100 to 200 degrees for several hours, the round surface of thecommon resin layer 35 is cut to a flat surface by a dicing device with adicing blade. Specifically, the round surface of the common resin layer35 is scraped off by the dicing blade to achieve a constant height fromthe board 21. In this step, the thickness of the common resin layer 35is set to 0.3-1.0 mm. The flat surface extends to the edges of thecommon resin layer 35 such that when outermost semiconductor chips 33are separated into individual semiconductor devices, they have resinlayer contours which meet a standardized package size requirement. Ofvarious available dicing blades having different thicknesses, arelatively thick dicing blade is used to scrape the round surface of thecommon resin layer 35 repeatedly a plurality of times to develop a flatsurface.

[0039] Alternatively, before the dropped liquid resin 35 is hardened, aflat member may be pressed against the round surface of the common resinlayer 35 to flatten the surface into a flat and horizontal surfaceparallel to the board 21. Thereafter, the dropped liquid resin 35 may behardened.

[0040] 5TH STEP (FIG. 8A)

[0041] The board 21 is turned upside down, and a dicing sheet 50 (e.g.,trade name: UV SHEET manufactured by Lintec Corp.) is applied to thesurface of the common resin layer 35. Since the surface of the commonresin layer 35 has been flattened into the flat and horizontal surfaceparallel to the board 21, the board 21 is not tilted by the dicing sheet50 applied to the surface of the common resin layer 35, and hence ismaintained at a desired level of horizontal accuracy.

[0042] 6TH STEP (FIG. 8B)

[0043] The common resin layer 35 is severed into segments containing therespective device carrier areas 20 to separate individual semiconductordevices by a dicing device. Specifically, a dicing blade 36 is used tocut off the common resin layer 35 and the board 21 simultaneously alongthe dicing lines 24 to produce separate semiconductor devices on therespective device carrier areas 20. In the dicing process, the dicingblade 36 is thrust to such a depth as to reach the surface of the dicingsheet 50 thereby to cut off the common resin layer 35 and the board 21.At this time, the dicing device automatically recognizes alignment marksthat can be observed from the back of the board 21, e.g., through holesdefined in peripheral areas of the board 21 or portions of the platedlayer of gold, and uses the alignment marks as a positional reference inthe dicing process. The external electrodes 31 a, 31 b, 31 c, 31 d andthe islands 25 are patterned such that they are held out of contact withthe dicing blade 36. This is to prevent the plated layer of gold frombeing burred by the dicing blade 36 as much as possible in view of arelatively low level of cuttability of the plated layer of gold.Therefore, the dicing blade 36 and the plated layer of gold are broughtinto contact with each other at the first and second joint arms 27, 28which are provided for electrical connection.

[0044]FIGS. 9A and 9B show in perspective a semiconductor devicefabricated by the above successive steps.

[0045] Each package of the semiconductor device has four sides definedby cut edges of the resin layer 35 and the board 21, an upper surfacedefined by the flat surface of the resin layer 35, and a lower surfacedefined by the back of the board 21.

[0046] The semiconductor device has a size including a length of 1.0 mm,a width of 0.6 mm, and a height of 0.5 mm. The board 21 is covered withthe common resin layer 35, sealing the semiconductor chip 33. Thesemiconductor chip 33 has a thickness of about 150 μm. The island 25 andthe leads 26 are spaced or retracted from the edges of the package, withcut edges of the first and second joint arms 27, 28 being exposed onedges of the package.

[0047] The external electrodes 31 a-31 d are disposed at the respectivefour corners of the back of the board 21, and each have a size of about0.2×0.3 mm. The external electrodes 31 a-31 d are vertically(horizontally) symmetrical with respect to central lines of the packagecontour. Since the symmetrical layout of the external electrodes 31 a-31d makes it difficult to distinguish their polarities from each other, itis preferable to form recesses in or apply printed indicia to thesurfaces of the external electrodes 31 a-31 d to provide marksindicating their polarities.

[0048] Because semiconductor devices thus fabricated are packagedtogether by the resin layer, the amount of synthetic resin which wouldbe wasted and the cost of the synthetic resin used are smaller than ifthe semiconductor devices were individually packaged by conventionalmethod. As no lead frames are used, the outer profile of the package ismuch smaller than if the package were fabricated according to theconventional transfer molding process. Since the terminals for externalconnection are mounted on the back of the board 21 and do not projectfrom the package, the package has a reduced mounting area.

[0049] In the above fabrication process, the dicing sheet 50 is appliedto the common resin layer 35, rather than the board 21. If the dicingsheet 50 were applied to the board 21, the adhesive of the dicing sheet50 would be left on the surfaces of the electrodes 31 a-31 d when thesemiconductor devices are removed from the dicing sheet 50. If asemiconductor device with adhesive deposits left thereon were suppliedto an automatic mounting apparatus, then the solderability of theelectrodes 31 a-31 d would be impaired when the semiconductor device ismounted on a printed-circuit board. Dust particles that would tend to beapplied to the electrodes 31 a-31 d because of the adhesive depositswould also pose a problem. According to the present invention, the abovedrawbacks are not present because the dicing sheet 50 is applied to theside of common resin layer 35.

[0050] Furthermore, since the dicing sheet 50 is applied to the flat andhorizontal surface of the common resin layer 35, the board 21 ismaintained at a desired level of horizontal accuracy which is the sameas if the dicing sheet 50 were applied to the board 21.

[0051] In the illustrated embodiment, the three-terminal activecomponent is sealed and the four external electrodes are formed.However, the principles of the present invention are also applicable tothe fabrication of a semiconductor device having two sealedsemiconductor chips or a sealed integrated circuitchip.

[0052] The method according to the present invention can produce apackage structure which is smaller than semiconductor devices using alead frame. Since no lead terminals project from the package, thepackage has a reduced mounting area and can be mounted at a highdensity.

[0053] The cost of the fabrication process is highly reduced because anymolds with cavities are required for sealing semiconductor chips.

[0054] After the surface of the common resin layer 35 is flattened, thedicing sheet 50 is applied to the flat surface of the common resin layer35, and then the common resin layer 35 is severed into segmentscontaining the respective device carrier areas 20 to separate individualsemiconductor devices by a dicing device. Therefore, no adhesive of thedicing sheet 50 is applied to the surfaces of the electrodes 31 a-31 d.

[0055] Although a certain preferred embodiment of the present inventionhas been shown and described in detail, it should be understood thatvarious changes and modifications may be made therein without departingfrom the scope of the appended claims.

What is claimed is:
 1. A method of fabricating a semiconductor device,comprising the steps of: preparing a board with a plurality of devicecarrier areas thereon; fixing semiconductor chips respectively to saiddevice carrier areas; covering said semiconductor chips fixed to saiddevice carrier areas with a common resin layer; flattening a surface ofsaid common resin layer; applying a dicing sheet to the flattenedsurface of said common resin layer; and separating said board and saidcommon resin layer into segments including the device carrier areasthereby to produce individual semiconductor devices by dicing from aback of said board.
 2. A method according to claim 1, further comprisingthe step of: placing an electrode pattern serving as external electrodesof the semiconductor chips on said back of said board, said electrodepattern being spaced inwardly from dicing lines along edges of saidsegments so as to be kept out of contact with a dicing blade along saiddicing lines.
 3. A method according to claim 1, wherein an electricallyconductive pattern is formed on a surface of said board for fixing saidsemiconductor chip, and another electrically conductive pattern isformed for external connection at back of said board which connects tosaid conductive pattern via through hole filled with conductivematerial.
 4. A method according to claim 1, wherein said board comprisesof ceramics or glass epoxy.
 5. A method according to claim 1, whereinsaid resin layer comprises of epoxy resin.